The present invention pertains to the field of integrated circuit devices and manufacturing processes for the same. More particularly, this invention relates to the formation of high quality multiple thickness oxide layers on a silicon wafer substrate.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
High voltage circuit elements such as program and erase transistors are usually formed on a wafer substrate with a relatively thick gate oxide layer. Such relatively thick gate oxide layers are usually required to prevent transistor circuit breakdown in such a high voltage environment. On the other hand, it is preferable that the low voltage circuitry is implemented with relatively thin gate oxide layers on the wafer substrate. Such thin gate oxide layers typically increase the speed of such circuit elements having relatively short gate lengths and thin oxide layers typically provide increased operation speeds.
In addition, as process technologies evolve toward shorter and shorter gate lengths it is desirable to reduce the thickness of the gate oxide layer even further in order to achieve greater operating speed. However, some circuit elements contained on such integrated circuit devices may not be scalable.
Non-volatile memory devices, such as flash EEPROMs require the formation of flash memory cells that include tunnel oxide layers on the wafer substrate. Such tunnel oxide layers may be thinner than high voltage oxide layers on the wafer substrate. However, such tunnel oxide layers usually cannot be scaled down in thickness in the same manner as low voltage oxide layers. Such flash memory cells, for example, typically suffer from significant endurance and data retention problems if the tunnel oxide layers are too thin.
Therefore, non-volatile memory devices can usually benefit from the formation of differing oxide thicknesses on the same wafer substrate. Transistors with relatively thick select gate oxide layers can accommodate high voltage program and erase operations while logic transistors with relatively thin gate oxide layers can yield speed advantages as process technologies evolve toward smaller circuit element dimensions. In addition, the thickness of tunnel oxide layers for flash memory cells can be scaled for reliability independent of the gate dimensions and oxide thickness of the high and low voltage transistors.
One method of forming high quality multiple thickness oxide layers involves multiple masking and oxide formation steps. For example, a first oxide layer, usually the thickest oxide layer, is initially grown on the wafer substrate. Thereafter, a layer of photoresist is formed on the first oxide layer. A pattern is formed on the photoresist layer by exposing the photoresist through a mask. The photoresist is then developed and removed, leaving a portion of the oxide layer exposed. Subsequently, the first oxide layer is etched and the remaining photoresist is stripped. A second layer of oxide is then grown on the wafer substrate. The second oxide layer forms a thin oxide layer on the wafer substrate while a thicker oxide layer is formed by the combination of the first and second oxide layers. This process can be repeated to form additional oxide layers with various thicknesses throughout the process flow.
During and after development of the photoresist layer, the unmasked or exposed portion of the oxide layer may become contaminated. For example, a thin film, undetectable on visual inspection, may form on the exposed portion of the oxide layer. This film may consist of photoresist residue such as dried developer and undissolved pieces of photoresist. Thus, it is usually necessary to subject the unmasked portion of the oxide layer to a cleaning or descumming process to remove the resist residue. The unmasked or exposed portion of the oxide layer is often descummed or cleaned with O2, O2/N2 or O2/N2xe2x80x94H2 chemistries in a barrel asher or a downstream single wafer asher.
Although the descum process is relatively short in order to avoid any surface damage to the exposed oxide layer, the descum process itself leaves contaminants on the oxide layer. The contaminants appear as dark spots on the oxide layer under a high-resolution scanning electron microscope (SEM) as shown in FIG. 1. An analysis of the dark spots shows that they consist of sulfur compounds and small hydrocarbons, most likely photo active compound, left over from the development of the photoresist. These dark spots or defects on the surface of the exposed oxide layer interact with subsequent processing steps, which creates processing problems and degrades reliability and yield.
For example, when a wet oxide etch is carried out after descum to remove the exposed portion of an oxide layer, the oxide layer under the dark spots cannot be completely removed. Thus, the dark spots act as a micromask on the exposed portion of the oxide layer. As a result of the dark spots, a subsequently grown oxide layer may not be uniform because the initial oxide layer is not completely removed.
Therefore, it would be desirable to have a process for removing these dark spots or defects when forming multiple thickness gate and tunnel oxide layers in order to achieve a higher overall yield of acceptable wafers.
A method of forming uniform oxide layers by reducing descum induced defects is disclosed. The method comprises reactive ion etching (RIE) a semiconductor substrate, which includes a wafer, an oxide layer on the wafer and a developed photoresist mask on the oxide layer. After reactive ion etching the substrate, the oxide layer is etched.
Other features and advantages of the present invention will be apparent from the detailed description of the invention.